EDN

Intilop’s 16K Concurrent TCP & UDP Session Hardware Accelerator Core (TOE & UOE) Now Available for Immediate Data Center Deployment

MILPITAS, Calif., Oct. 22, 2014 /PRNewswire/ — Intilop, Inc. a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper Performance Complex Networking Protocol ...
EDN

Intilop releases yet another first: A Full TCP & UDP Host-Side Application interface for Altera & Xilinx FPGAs for Software’s use that is implemented in low latency ...

This deployment-ready, pre-verified FPGA system solution provides networking OEMs Ultra-low-latency and Hyper-performance for all networking equipment segments that have to process TCP, UDP and IGMP ...
Design-Reuse

Intilop delivers their Enhanced 16 Thousand TCP & UDP Session Hardware Accelerator on Altera and Xilinx FPGAs targeted towards all Hyper Performance Networking Systems

Intilop, Inc. a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper Performance Complex Networking Protocol Accelerators, Mega IP Cores, Systems and Solutions since ...
Design-Reuse

Intilop Releases Altera's Stratix IV/V FPGA platform with their 16K Concurrent-TCP-Session Hardware Accelerator

The Complete ‘Full TCP stack’ pre-ported and verified on Altera Stratix IV/V Platform with Intilop’s 6 th generation industry leader, delivers ‘77 nanosecond TCP processing times and 97% TCP ...